The ongoing advancements in integrated circuit (IC) technologies have led to the use of lower supply voltages to operate the IC's. Lower supply voltages help cope with a problem of hot carrier induced, limited lifetime for the IC's. Designing the IC's with lower supply voltages requires the use of very thin gate oxides. The thickness of the gate oxides influences the amount of drive current that is generated. The thinner the gate oxide layer, the more drive current is generated, which thereby increases the speed of the circuit. The gate oxides (e.g. silicon dioxide) may have a thickness of less than 3 nanometers, and further advancements will allow the gate oxide thickness to scale down even further. The lower supply voltages also allow the use of silicon controller rectifiers (SCRs) with very low holding voltages (e.g. 1.5-2.0V) without introducing a risk of latch-up. The thin gate oxides, which are used in conjunction with low supply voltages, require extreme limitation of transient voltages during an ESD current.
FIG. 1 depicts a schematic diagram of a prior art diode turn-on SCR or diode triggered SCR (DTSCR) protection device 100 to preferably provide ESD protection, as illustratively provided in U.S. Pat. No. 6,786,616 B2. In particular, the DTSCR 100 consists of an NPN transistor with highly doped N+ and P+ regions in lowly doped N-well, forming an anode 102 and an PNP transistor with highly doped N+ and P+ regions in lowly doped P-well or P substrate forming a cathode 104. The anode 102 is connected to a pad (not shown) and to one side of a resistor 106. The resistor 106 presents the resistance of the N-well or an external resistor which is seen at the base of PNP transistor. The cathode 104 is connected to a ground (not shown) and to one side of a resistor 108. The resistor 108 represents the resistance of the P-well or an external resistor which is seen at the base of the NPN transistor. Also included is a first trigger tap or gate G1 110 to the base of NPN and a second trigger tap or gate G2 112 to the base of the PNP. Also included is a string of diode chain 114 connected to the trigger tap G1 110 or to the trigger tap G2 112 as shown in FIG. 1. The diode chain 114 injects current in either the Pwell P+ region, to forward bias G1-Cathode junction or extracts current from the Nwell N+, to forward bias the Anode-G2 junction. This in turn triggers the SCR 100 So, in previous art, a diode chain such as one shown in FIG. 1 is used to trigger an SCR.
In the previous art the diode string is placed and created externally, separate to the SCR. The diode string was optimized for triggering the SCR for the ESD-current capability. Therefore, the diode string will conduct only trigger current and the SCR will only conduct ESD-current.
Therefore, there is a need in the art to provide a novel means for constructing an ESD device with using the advantages of the current capability of the diode string and the trigger capability of the SCR.